The present invention pertains to a frequency synthesizer. More specifically, the present invention pertains to a frequency synthesizer that can accurately compensate for ripple current.
For a cellular phone of the multi-channel access type, in order to shift the current frequency to a vacant channel, there must be a frequency synthesizer that allows high-speed lock-up.
In FIG. 3, 101 represents a conventional frequency synthesizer used in a fractional frequency division type PLL (Phase Locked Loop) circuit.
Said frequency synthesizer 101 is set inside a semiconductor integrated circuit that forms the transceiver of the cellular phone. It has the following parts: oscillator 131, frequency divider 132, reference clock signal generator 133, phase comparator 134, charge pump circuit 135, low-pass filter 136, compensation circuit 137, and controller 138. In said oscillator 131, an external output signal OUT is generated at the prescribed frequency, and the external output signal OUT is output to frequency divider 132 and the other circuits in the semiconductor integrated circuit where said frequency synthesizer 101 is set.
Frequency divider 132 frequency divides the external output signal OUT that is input, and it generates a comparison signal that is output to phase comparator 134. Said phase comparator 134 compares the phase of the comparison signal input from frequency divider 132 with the phase of the reference clock signal input from reference clock signal generator 133, and outputs a signal corresponding to the phase difference to charge pump circuit 135. Based on the signal corresponding to the input phase difference, charge pump circuit 135 creates a positive/negative output current flow and this output current is output as a control signal through low-pass filter 136 to oscillator 131.
Based on the input control signal, oscillator 131 changes the frequency of external output signal OUT, and it operates such that the phase of the comparison signal comes into sync with the phase of the reference clock signal. As a result, the frequency of external output signal OUT is equal to the frequency of the reference clock signal times the frequency division value of frequency divider 132.
Said frequency divider 132 is controlled by controller 138, and the frequency division value is made to change periodically. As an example, when the frequency of the reference clock signal is 200 kHz, suppose the frequency division value is 5000 for the period of 7 cycles (35 xcexcsec), and it is 5001 for the period of 1 cycle period (5 xcexcsec). In this case, the average frequency division value for the 8 cycles is 5000.125(=5000+xe2x85x9), and the frequency of external output signal OUT is locked to 1000025 kHz, that is, the reference clock signal times the average frequency division value.
Suppose the frequency division value is 4000 for 6 cycles, and 4001 for 2 cycles during 8 cycles, the average frequency division value is 4000.25, and the frequency of external output signal OUT becomes 800.050 MHz.
In this way, when the average frequency division value has a value with precision to after the decimal point, it is possible to use high frequencies such as 800 MHz, 1 GHz, etc. with narrow channel intervals of 25 kHz, 12.5 kHz, etc.
However, when the frequency division value is changed periodically as aforementioned, even after the external output signal OUT is locked at the desired frequency, the phase of the comparison signal and the phase of the reference clock signal are not in sync, and there is a phase difference. Consequently, the control signal output from phase comparator 134 contains a ripple current.
In FIG. 4, a indicates the waveform of the comparison signal input from frequency divider 132 after external output signal OUT is locked as the frequency division value changes between N and N+1, b represents the waveform of the reference clock signal, and c represents the waveform of the ripple current in the control signal output from charge pump circuit 135 due to the fact that the phase of the comparison signal and the phase of the reference clock signal are not in sync.
The ripple current contained in the control signal generates spurious signals in the external output signal. This not only degrades the reception characteristics of cellular phones and other communications equipment, but it also becomes a component that degrades transmission. It is a serious problem.
In this frequency synthesizer 101 there is a compensating circuit 137 having a DA converter 141 and a capacitor 142. DA converter 141 changes the voltage applied to capacitor 142, and it generates a compensating current having the same charge quantity as the ripple current yet having an opposite sign. The compensating current is superimposed onto the control signal output from charge pump circuit 135. The ripple current is cancelled out. As a result, an external output signal OUT having no spurious components is obtained.
The charge quantity of the ripple current that varies over time changes such that it becomes an integer times a prescribed theoretical unit charge quantity. The theoretical unit charge quantity indicates the product of the phase difference between the comparison signal and the reference clock signal and the output current of charge pump circuit 135.
As an example, as aforementioned, when the frequency of external output signal OUT is 1000025 kHz, suppose the output current of charge pump circuit 135 is a constant current of +1 mA or xe2x88x921 mA, the following Qr becomes the unit charge quantity:
Qr=(xe2x85x9)xc3x97(1/1000025 kHz)xc3x971 mAxc3x97xc2xd=62.5xc3x9710xe2x88x9215(Coulomb)xe2x80x83xe2x80x83(101)
Then, ripple current is generated at the same period as that of the reference clock signal with charge quantities from xc2x11 up to xc2x17 times said unit charge quantity Qr (xc2x17Qr) in the following order +7Qrxe2x86x92+5Qrxe2x86x923Qrxe2x86x921Qrxe2x86x92xe2x88x921Qrxe2x86x92xe2x88x923Qrxe2x86x92xe2x88x925Qrxe2x86x92xe2x88x927Qr.
In order to compensate for such ripple current, if the capacitance of capacitor 142 is C1, voltage Ve from the following formula:
Ctxc2x7Ve=Qrxe2x80x83xe2x80x83(102)
is used as a unit by DA converter 141 to convert voltage Vd applied to capacitor 142 in the following magnitudes and order: xe2x88x927Ve, xe2x88x925Ve, xe2x88x923Ve, xe2x88x921Ve, +1Ve, +3Ve, +5Ve, +7Ve, which results in a compensating current having the same charge quantity as that of the ripple current but having an opposite sign. The compensating current is superimposed onto the output current of charge pump circuit 135. In this way, the ripple current can be cancelled out.
As explained above, in said frequency synthesizer 101, a compensating current is preset so that by superimposition, the ripple current can be compensated for correctly. However, when the ripple current that is actually output varies due to certain reasons, such as variation in the circuit constants of the circuit elements, etc., it is impossible to compensate for the ripple current accurately.
A general object of the present invention is to solve the aforementioned problems of the conventional methods by providing a device which can accurately compensate for the ripple current.
The object and other features of the invention are attained, in accordance with one aspect of the invention by a frequency synthesizer characterized by the fact that it has he following parts: an oscillator, wherein the frequency of the output oscillating signal controlled corresponding to a control signal; a frequency divider of the fractional frequency dividing type which frequency-divides the aforementioned oscillating signal and generates a comparison signal; a reference clock signal generator which generates a reference clock signal; a phase comparator which compares the phase of said comparison signal and the phase of said reference clock signal and outputs a phase difference signal; a charge pump circuit which outputs current corresponding to the aforementioned phase difference signal; a low-pass filter which removes the high-frequency component of the current output from the aforementioned charge pump circuit and sends the resulting signal as the aforementioned control signal to the aforementioned oscillator; a switching circuit which is connected between the output terminals of the aforementioned charge pump circuit and the aforementioned low-pass filter; a compensating circuit which outputs a compensating current for compensating the ripple current contained in the aforementioned control signal to the output terminal of the aforementioned charge pump circuit; and a correcting circuit which detects the current at the output terminal of the aforementioned charge pump circuit and corrects the aforementioned compensating current.
In another aspect of the invention, the correcting circuit detects the current at the output terminal of the aforementioned charge pump circuit corresponding to the period of the aforementioned fractional frequency division of the aforementioned frequency divider, and the aforementioned switching circuit performs ON/OFF control corresponding to the period of the aforementioned fractional frequency division.
With the aforementioned constitution, in the present invention, the oscillating signal output from the oscillator is frequency divided by a frequency divider while the frequency division value is changed periodically, and a comparison signal and reference clock signal are output to the phase comparator.
The phase comparator operates a charge pump circuit and it compares the phase of the input reference clock signal with the phase of the comparison signal. Then, corresponding to the phase difference, a constant positive or negative output current flows from the charge pump circuit, high-frequency components are removed by a low-pass filter, and a control signal is generated.
The control signal is input to the oscillator, and based on this control signal, the oscillator changes the frequency of the oscillating signal in the direction that reduces the phase difference between the reference clock signal and the comparison signal. As a result, the frequency of the oscillating signal becomes the frequency of the reference clock signal times the average frequency division value.
In this frequency synthesizer, a compensating circuit is set, and a compensating current, which has a sign opposite to that of the ripple current in the output current of the charge pump circuit, is generated. When the compensating current is superimposed on the output current, the ripple current is cancelled out, and the spurious components are removed from the oscillating signal.
When the compensating current is set, in the prior art, the current level of the ripple current is determined beforehand, and the compensating current is preset so that it can accurately cancel out the ripple current. When the ripple current varies due to certain reasons, it becomes impossible to cancel out of the ripple current accurately.
According to the present invention, the frequency synthesizer has a compensating circuit. In the compensating circuit, the output current with the superimposed compensating current is detected directly. Based on the detection result of the detected output current, it is possible to adjust the current level of the compensating current. Consequently, even when the ripple current varies due to certain reasons, the current level of the compensating current can still be adjusted based on the current level of the varying ripple current.
Consequently, it is possible to adjust the current level of the compensating current corresponding to variations in the ripple current, and to cancel the ripple current correctly.
Also, in one aspect of the present invention the frequency synthesizer has a switching circuit, and the switching circuit can cut off between the output of the charge pump circuit and the input of the low-pass filter. At the desired timing, the compensating circuit detects the output current with the superimposed compensating current. Consequently, when the output of the charge pump circuit and the input of the low-pass filter are cut off from each other, it is possible to detect the output current with the superimposed compensating current.
Also, when the output current of the charge pump circuit is output through the low-pass filter, the ripple current is integrated by the low-pass filter. Consequently, the periodically varying ripple current is averaged, making it hard to detect. According to the present invention, it is possible to detect the output current of the charge pump with the superimposed compensating current directly. Consequently, it is possible to detect the current with a compensating current superimposed on a ripple current that has not been integrated or averaged. Consequently, it is possible to detect the ripple current reliably.
In addition, the ripple current usually varies periodically. If the overall ripple current level is low, because the output current is detected at a time when the current level of the ripple current is low, the detected output current is very small, and it may not be detectable in extreme cases. In this case, it is determined that there is no ripple current, and the ripple current cannot be cancelled out accurately. In the present invention, because it is possible to detect the output current with the superimposed compensating current at the desired timing. Consequently, it is possible to detect the output current at a time when the current level of the ripple current is higher.
Consequently, even in the case when the overall current level of the ripple current is low and it is hard to detect, the detected output current is still relatively large. Consequently, it is easy to detect the ripple current, and it is possible to detect the ripple current with high accuracy.